1. RCC: Reset and Clock Control
The RCC is the foundational peripheral responsible for managing the MCU's power-on state and generating the precise, stable clock signals required by all other components. A correctly configured clock tree is the first step in any embedded application.
Clock Tree and SYSCLK Generation
The primary goal of the RCC is to produce a high-speed, stable System Clock (SYSCLK). This is typically achieved by selecting a reliable source (like an external crystal) and multiplying its frequency with the Phase-Locked Loop (PLL).
Key Concept: Clock Security System (CSS)
Most modern MCUs include a CSS. If the HSE (external crystal) fails for any reason, the CSS automatically switches the system clock back to the internal HSI and triggers an interrupt (a Non-Maskable Interrupt, or NMI). This is a critical fail-safe to prevent a total system crash if the primary clock source is lost.
HSI
16 MHz RC
HSE
8 MHz Crystal
PLL MUX
Clock Selector
PLL (e.g., x9)
Frequency Multiplier
SYSCLK
72 MHz System Clock
2. Bus Architecture & Matrix
Modern MCUs use a sophisticated bus matrix to connect multiple "master" devices (like the CPU and DMA) to multiple "slave" devices (like memory and peripherals). This allows for simultaneous data transfers, significantly improving system performance.
Bus Matrix Explorer
The diagram below illustrates how different masters can access different slaves concurrently via the high-speed AHB bus matrix. The slower APB buses branch off the AHB to service lower-speed peripherals.
Key Concept: Bus Arbitration
What happens if the CPU and DMA try to access SRAM at the same time? The bus matrix contains an **arbiter** that resolves this conflict. It uses a priority scheme (e.g., round-robin or fixed priority) to grant access to one master while temporarily stalling the other. This process is handled entirely in hardware.
3. General-Purpose Timers ⏱️
Timers are the workhorses of embedded systems, enabling precise event scheduling, signal generation, and measurement without consuming CPU cycles.
Core Components & Frequency Calculation
A timer's behavior is defined by its core registers: the **Prescaler (PSC)** divides the input clock, and the **Auto-Reload Register (ARR)** sets the counting period.
Resulting Update Frequency:
1000.00 Hz
Key Operating Modes
Timers can be configured in various modes. Below are interactive demonstrations and pseudo-code examples.
Counter Modes
Timers can count up, down, or in a center-aligned mode. This affects when the overflow event occurs and is crucial for applications like generating symmetrical PWM for motor control.
CNT: 0 / ARR: 100
PWM Mode
Generates a signal with a variable duty cycle. Ideal for controlling motor speed or LED brightness.
// PWM Mode Pseudo-code Example
TIM3->PSC = 0; // No prescaling for max frequency
TIM3->ARR = 255; // Set 8-bit resolution (0-255)
TIM3->CCR1 = 128; // Set compare value for 50% duty cycle
// Configure Channel 1 for PWM Mode 1
TIM3->CCMR1 |= (6 << 4); // OC1M = 110
TIM3->CCER |= (1 << 0); // CC1E = 1
TIM3->CR1 |= (1 << 0); // CEN = 1
Advanced Timer Features
DMA Integration
Timers can trigger DMA transfers automatically. For example, a timer update event can trigger a DMA request to move the next value from a buffer in memory directly into the timer's `CCR` register. This is essential for generating complex waveforms (like audio) without any CPU intervention.
Master/Slave Synchronization
Timers can be linked together. A "master" timer can be configured to start, stop, or reset one or more "slave" timers. This is critical for applications like three-phase motor control where multiple PWM signals must be perfectly synchronized.
4. Watchdog Timers 🐕
A watchdog is a critical safety peripheral that resets the MCU if the software freezes, ensuring the system can automatically recover from faults without manual intervention.
Independent Watchdog (IWDG)
The IWDG runs on its own internal clock (LSI), making it robust against main clock failures. Its timeout is calculated as `Timeout = (Prescaler * Reload_Value) / LSI_Clock`.
Window Watchdog (WWDG)
The WWDG is clocked from the main APB clock and requires a refresh within a configured time "window". A refresh outside this window (too early or too late) causes a reset.
Best Practice
Pet the watchdog in your main application loop (`while(1)`) only after all critical tasks for that iteration have completed successfully. This ensures that a reset occurs if any single task hangs.